For this mode, the mode select input M is at logic 0 (M=0).ĭOWN counting mode (M=1) − If M = 1, then the Q bar output of the preceding FF is connected to the next FF. UP counting mode (M=0) − The Q output of the preceding FF is connected to the clock of the next stage if up counting is to be achieved. But the clock to every other FF is obtained from (Q = Q bar) output of the previous FF. The LSB flip-flop receives clock directly.
So either T flip-flops or JK flip-flops are to be used. In the UP/DOWN ripple counter all the FFs operate in the toggle mode. A combinational circuit is required to be designed and used between each pair of flip-flop in order to achieve the up/down operation. A mode control (M) input is also provided to select either up or down mode. Up counter and down counter is combined together to obtain an UP/DOWN counter.
On application of the next clock pulse, Q A will change from 1 to 0 as Q B will also change from 1 to 0.ĭepending on the way in which the counting progresses, the synchronous or asynchronous counters are classified as follows − On application of the third falling clock edge, FF-A will toggle from 0 to 1 but there is no change of state for FF-B. On the arrival of second negative clock edge, FF-A toggles again and Q A changes from 1 to 0.īut at this instant Q A was 1. Logical Diagram Operation S.N.Īs soon as the first negative clock edge is applied, FF-A will toggle and Q A will change from 0 to 1.īut at the instant of application of negative clock edge, Q A, J B = K B = 0. The J B and K B inputs are connected to Q A. The J A and K A inputs of FF-A are tied to logic 1. If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a counter is called as synchronous counter. Q BQ A = 00 after the fourth clock pulse. Hence it toggles to change Q B from 1 to 0. This negative change in Q A acts as clock pulse for FF-B. On the arrival of 4th negative clock edge, FF-A toggles again and Q A becomes 1 from 0. So Q B does not change and continues to be equal to 1. Since this is a positive going change, FF-B does not respond to it and remains inactive. On the arrival of 3rd negative clock edge, FF-A toggles again and Q A become 1 from 0. Q BQ A = 10 after the second clock pulse. So it will also toggle, and Q B will be 1. The change in Q A acts as a negative clock edge for FF-B. On the arrival of second negative clock edge, FF-A toggles again and Q A = 0. There is no change in Q B because FF-B is a negative edge triggered FF. Since Q A has changed from 0 to 1, it is treated as the positive clock edge by FF-B. Initially let both the FFs be in the reset stateĪs soon as the first negative clock edge is applied, FF-A will toggle and Q A will be equal to 1. External clock is applied to the clock input of flip-flop A and Q A output is applied to the clock input of the next flip-flop i.e. But we can use the JK flip-flop also with J and K connected permanently to logic 1. The logic diagram of a 2-bit ripple up counter is shown in figure. It is a group of flip-flops with a clock signal applied. Counter is the widest application of flip-flops.
A digital circuit which is used for a counting pulses is known counter.